Search - rom verilog

[ELanguage] rs-codec-8-4

Description: encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license -encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien - search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data - rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Platform: | Size: 44917 | Author: zs8292 | Hits:

[Other resource] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输，值得学习。
Platform: | Size: 928622 | Author: alison | Hits:

[VHDL-FPGA-Verilog] 用FPGA实现DDS信号发生及用MODELSIM仿真

Description: 该工程是用verilog编写，FPGA内部产生ROM及ADD加法器。ROM中存正弦波信号。文件夹中还包含modelsim仿真。
Platform: | Size: 2527046 | Author: zhengguo22 | Hits:

[VHDL-FPGA-Verilog] VHDL语言100例详解

Description: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Platform: | Size: 6633472 | Author: 穆群生 | Hits:

[VHDL-FPGA-Verilog] ROM

Description: 使用Verilog语言编写的ROM，根据ROM逻辑，自己写的一个ROM，并仿真实现功能-read only memory
Platform: | Size: 4382720 | Author: 舒占军 | Hits:

[VHDL-FPGA-Verilog] rom

Description: ROM模式的实现机制，基于verilog语言。-Implementation mechanism of ROM model, based on Verilog language.
Platform: | Size: 1024 | Author: mxc | Hits:

[e-language] Verilog-HDL

Description: 本课程设计在EDA开发平台上利用Verilog HDL语言设计数控分频器电路，利用数控分频的原理设计乐曲硬件演奏电路，并定制LPM-ROM存储音乐数据，-This course is designed to take advantage of the EDA Verilog HDL language development platform NC divider circuit design, the use of CNC dividing principles music playing hardware circuit design and customize LPM-ROM to store music data,
Platform: | Size: 1049600 | Author: 李永科 | Hits:

[Other] Verilog-135-classic-design

Description: verilog的135个经典设计，适合初学者自学。内有FIR、数字钟、交通灯、串转并、ram、rom等等常用模块的完整verilog代码，以及测试程序。还有基本的设计源码-verilog of 135 classic design, suitable for beginners learning. There are FIR, complete verilog code for a digital clock, traffic lights, and turn string, ram, rom, etc. commonly used modules, and test procedures. There are basic design source
Platform: | Size: 116736 | Author: 王凌 | Hits:

[VHDL-FPGA-Verilog] verilog-midi-reader-master

Description: MIDI file parser that converts song and lyric data to Verilog ROM format for use on an FPGA
Platform: | Size: 22528 | Author: 小海豚 | Hits:

[VHDL-FPGA-Verilog] 31-x-8-ROM-master

Description: Verilog module for a ROM. The rom needs to be able to hold 32 unsigned Integers each 8 Bits. Thus it must have32 address lines.
Platform: | Size: 1024 | Author: 小海豚 | Hits:

[VHDL-FPGA-Verilog] ROM

Description: FPGArom的IP核使用及仿真,Verilog语言，非常详细-IP core and use of simulation FPGArom, Verilog language, very detailed
Platform: | Size: 5943296 | Author: 杨福廷 | Hits:

[VHDL-FPGA-Verilog] ROM

Description: 使用verilog语言实现对altera下cycloneII系列FPGA的片上ROM的创建，读写，调用IP核-Use verilog language to achieve altera under the cycloneII series FPGA on-chip ROM to create, read and write, call IP core
Platform: | Size: 36864 | Author: 张仑仑 | Hits:

[VHDL-FPGA-Verilog] 10_rom_test

Description: rom ip核的配置，以及测试文件，适合初学者使用。(ROM IP core configuration, as well as test files, suitable for beginners to use.)
Platform: | Size: 4237312 | Author: 声声不洗 | Hits:

[VHDL-FPGA-Verilog] rom_test

Description: rom读写实验，实现FPGA内部rom数据存取(rom read and write,this is a good document for study FPGA verilog)
Platform: | Size: 4245504 | Author: konan007 | Hits:

[VHDL-FPGA-Verilog] ARM_SOC

Description: ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM kernel leads to the JTAG interface, can connect the debugger to debug with keil-MDK!)
Platform: | Size: 688128 | Author: ldz13180882132 | Hits:

[VHDL-FPGA-Verilog] RS(204,188)译码器的设计

Description: RS(204,188)译码器说明原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_power.mif（ROM初始化文件）。仿真波形： rs_decoder.vwf。(RS (204188) decoder explanation Original document: Rs_decoder.v (top level file), SyndromeCalc.v (Computational adjoint), BM_KES.v (BM solving key equations). Forney.v (Forney algorithm for error sample), CheinSearch.v (search wrong location), ff_mul.v (finite field multiplication). ROM and initialization files: Rom_inv.v (inverse operation), rom_power.v (exponentiation operation). Rom_inv.mif (ROM initialization file), rom_power.mif (ROM initialization file). Simulation waveform: Rs_decoder.vwf.)
Platform: | Size: 15360 | Author: HelloFrank0 | Hits:

[VHDL-FPGA-Verilog] CIC

Description: 包括地址产生单元、数据查询单元（可以重新初始化rom中的数据，由matlab产生.coe文件替换）、积分单元、抽取单元、梳状滤波单元，对于初学者很有帮助(Including address generation unit, data query unit (data can be re-initialized in rom, generated by matlab. COE file replacement), integration unit, extraction unit, comb filter unit, is very helpful for beginners.)
Platform: | Size: 5120 | Author: 午后河流 | Hits:

[matlab] 数字滤波器的MATLAB与FPGA实现例程代码567

Description: 数字滤波器的MATLAB与FPGA实现——杜勇(配套光盘) 程序源码，配合电子书使用可以很好的学习数字滤波器的MATLAB与FPGA实现，完整代码，仿真良好，第5、6、7章((MATLAB and FPGA implementation of digital filter -- Du Yong (supporting CD-ROM) program source code, can learn matlab and FPGA implementation of digital filter well with e-book use, complete code, good simulation, the chapter 5 6 7))
Platform: | Size: 28524544 | Author: wanmei10 | Hits:

[matlab] Chapter_9

Description: 数字滤波器的MATLAB与FPGA实现——杜勇(配套光盘) 程序源码，配合电子书使用可以很好的学习数字滤波器的MATLAB与FPGA实现，完整代码，仿真良好，第9章((MATLAB and FPGA implementation of digital filter -- Du Yong (supporting CD-ROM) program source code, can learn matlab and FPGA implementation of digital filter well with e-book use, complete code, good simulation, the chapter 9))
Platform: | Size: 8313856 | Author: wanmei10 | Hits:

[VHDL-FPGA-Verilog] Memory Verilog

Description: ROM,RAM (dual port)- Verilog
Platform: | Size: 1585 | Author: gsrwork2017@gmail.com | Hits:

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[ELanguage] rs-codec-8-4

[Other resource] an_dcfifo_top_restored

[VHDL-FPGA-Verilog] 用FPGA实现DDS信号发生及用MODELSIM仿真

[VHDL-FPGA-Verilog] VHDL语言100例详解

[VHDL-FPGA-Verilog] ROM

[VHDL-FPGA-Verilog] rom

[e-language] Verilog-HDL

[Other] Verilog-135-classic-design

[VHDL-FPGA-Verilog] verilog-midi-reader-master

[VHDL-FPGA-Verilog] 31-x-8-ROM-master

[VHDL-FPGA-Verilog] ROM

[VHDL-FPGA-Verilog] ROM

[VHDL-FPGA-Verilog] 10_rom_test

[VHDL-FPGA-Verilog] rom_test

[VHDL-FPGA-Verilog] ARM_SOC

[VHDL-FPGA-Verilog] RS(204,188)译码器的设计

[VHDL-FPGA-Verilog] CIC

[matlab] 数字滤波器的MATLAB与FPGA实现例程代码567

[matlab] Chapter_9

[VHDL-FPGA-Verilog] Memory Verilog

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